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MHT CET 2021 (21 Sep, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2021 (21 Sep, Shift 2)

Q128MHT CET 2021 · 21 SEP · SHIFT 2Medium

Logic Gates

Combination of NAND gates is shown in the figure. It is equivalent to

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Answer: (c)

A NAND with tied inputs is a NOT: $y_1 = \bar A$ , $y_2 = \bar B$ .
Final NAND: $y = \overline{\bar A \cdot \bar B} = A + B$ .
So the answer is (c) OR gate.

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