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MHT CET 2024 (11 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2024 (11 May, Shift 2)

Q62MHT CET 2024 · 11 MAY · SHIFT 2Medium

Logic Gates

For the following digital logic circuit, the correct truth-table is

Figure

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Answer: (d)

  1. The triangle on A has a bubble, so it is a NOT gate: it gives Aˉ\bar{A}.
  2. NAND gate: Y=Aˉ⋅B‾=A+BˉY = \overline{\bar{A} \cdot B} = A + \bar{B}.
  3. Rows AB=00,01,10,11AB = 00, 01, 10, 11 give Y=1,0,1,1Y = 1, 0, 1, 1.
  4. This is table R, so the answer is (d).
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