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JEE Main 2026 (23 Jan, Shift 2) · Logic Gates

Logic Gates question from JEE Main 2026 (23 Jan, Shift 2)

Q20JEE Main 2026 · 23 JAN · SHIFT 2Medium

Logic Gates

For the given logic gate circuit, which of the following is the correct truth table?

Figure

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Answer: (a)

  1. OR gate gives n+mn + m; NAND gate: z=n⋅(n+m)‾z = \overline{n \cdot (n + m)}.
  2. Since n⋅(n+m)=nn \cdot (n + m) = n, z=nˉz = \bar{n}.
  3. So z=1z = 1 when n=0n = 0 and z=0z = 0 when n=1n = 1, whatever m is.
  4. Table (a) rows (0,0,1),(0,1,1),(1,1,0),(1,0,0)(0,0,1), (0,1,1), (1,1,0), (1,0,0) match, so the answer is (a).
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