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JEE Main 2025 (2 Apr, Shift 2) · Logic Gates

Logic Gates question from JEE Main 2025 (2 Apr, Shift 2)

Q46JEE Main 2025 · 2 APR · SHIFT 2Medium

Logic Gates

In the digital circuit shown in the figure, for the given inputs the PP and QQ values are:

Figure

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Answer: (c)

  1. Inputs 1,11, 1: NAND output =1⋅1‾=0= \overline{1\cdot 1} = 0.
  2. Both NOT gates give 00, so the OR gate output =0+0=0= 0 + 0 = 0.
  3. PP = AND(NAND output, OR output) =0⋅0=0= 0\cdot 0 = 0.
  4. QQ = NOR(0‾\overline{0}, OR output) =1+0‾=0= \overline{1 + 0} = 0.
  5. So the answer is (c) P=0,Q=0P = 0, Q = 0.
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