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MHT CET 2023 (11 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2023 (11 May, Shift 2)

Q91MHT CET 2023 · 11 MAY · SHIFT 2Medium

Logic Gates

In the digital circuit the inputs are as shown in figure. The Boolean expression for output $\mathrm{Y}$ is

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Answer: (c)

NAND gate gives $\overline{A \cdot B}$ ; NOT gate gives $\overline{C}$ .
OR gate: $Y = \overline{A \cdot B} + \overline{C}$ .
So the answer is (c).

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