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MHT CET 2026 (17 Apr, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2026 (17 Apr, Shift 2)

Q15MHT CET 2026 · 17 APR · SHIFT 2Medium

Logic Gates

In the following digital circuit, the output 'Y' will be '1' (one) for inputs 'A' and 'B' having values

Figure

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Answer: (d)

  1. Upper gate: P=A⋅B‾P = \overline{A \cdot B}. Lower gate: Q=Aˉ+B‾Q = \overline{\bar{A} + B}.
  2. Final NOR: Y=P+Q‾Y = \overline{P + Q}, so Y=1Y = 1 only when P=0P = 0 and Q=0Q = 0.
  3. P=0P = 0 needs A=1,B=1A = 1, B = 1. Then Q=0+1‾=0Q = \overline{0 + 1} = 0 as well.
  4. So the answer is (d) A=1,B=1A = 1, B = 1.
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