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MHT CET 2023 (12 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2023 (12 May, Shift 2)

Q90MHT CET 2023 · 12 MAY · SHIFT 2Medium

Logic Gates

In the following digital logic circuit, the output Y will be '1' for inputs

Figure

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Answer: (d)

  1. Upper gate: P=A⋅B‾P = \overline{A \cdot B}. Lower gate: Q=Aˉ+B‾Q = \overline{\bar{A} + B}.
  2. Final NOR: Y=1Y = 1 only when P=0P = 0 and Q=0Q = 0.
  3. P=0P = 0 needs A=B=1A = B = 1; then Q=0+1‾=0Q = \overline{0 + 1} = 0.
  4. So the answer is (d) A=1,B=1A = 1, B = 1.
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