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MHT CET 2024 (9 May, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2024 (9 May, Shift 1)

Q64MHT CET 2024 · 9 MAY · SHIFT 1Medium

Logic Gates

In the logic circuit diagram, when all the four inputs A,B,C,D\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D} are one, the outputs Y1,Y2,Y3\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3 are respectively (1,1,0)(1, 1, 0). When all the inputs A,B,C,D\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D} are changed to 'zero', the outputs Y1,Y2,Y3\mathrm{Y}_1, \mathrm{Y}_2, \mathrm{Y}_3 respectively change to

Figure

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Answer: (b)

  1. Y1=A+BY_1 = A + B, Y2=C⋅D‾‾=C⋅DY_2 = \overline{\overline{C \cdot D}} = C \cdot D, Y3=Y1+Y2‾Y_3 = \overline{Y_1 + Y_2}.
  2. Check: all inputs 1 give (1,1,0)(1, 1, 0), as stated.
  3. All inputs 0: Y1=0Y_1 = 0, Y2=0Y_2 = 0, Y3=0+0‾=1Y_3 = \overline{0 + 0} = 1.
  4. So the answer is (b) (0,0,1)(0, 0, 1).
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