Physics Circle home Student Login

Home›Chapters›Semiconductor Electronics PYQs›Logic Gates›Question 58

MHT CET 2024 (3 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2024 (3 May, Shift 2)

Q58MHT CET 2024 · 3 MAY · SHIFT 2Medium

Logic Gates

The combination of NAND gates is shown in figure (I) and (II). For the given inputs, the outputs in both the combinations are respectively.

Figure

Show answer and solution

Answer: (b)

  1. (I) Each input NAND has shorted inputs, so it is a NOT: 0‾=1\overline{0} = 1 and 0‾=1\overline{0} = 1.
  2. Final NAND: 1⋅1‾=0\overline{1 \cdot 1} = 0.
  3. (II) NAND followed by a NAND with shorted inputs (NOT) gives AND: Y=A⋅BY = A \cdot B.
  4. With both inputs HIGH, Y=1⋅1=1Y = 1 \cdot 1 = 1.
  5. So the answer is (b) 0, 1.
Report a mistake

More questions on Logic Gates