Logic Gates
The combination of NAND gates is shown in figure (I) and (II). For the given inputs, the outputs in both the combinations are respectively.
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Answer: (b)
- (I) Each input NAND has shorted inputs, so it is a NOT: and .
- Final NAND: .
- (II) NAND followed by a NAND with shorted inputs (NOT) gives AND: .
- With both inputs HIGH, .
- So the answer is (b) 0, 1.