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MHT CET 2026 (13 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2026 (13 May, Shift 2)

Q23MHT CET 2026 · 13 MAY · SHIFT 2Medium

Logic Gates

The following circuit is equivalent to

Figure

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Answer: (c)

  1. NOR gives A+B‾\overline{A + B}.
  2. NAND with joined inputs is a NOT gate, then another NOT: two inversions cancel.
  3. Y=A+B‾Y = \overline{A + B}.
  4. So the answer is (c) NOR gate.
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