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MHT CET 2024 (2 May, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2024 (2 May, Shift 1)

Q80MHT CET 2024 · 2 MAY · SHIFT 1Medium

Logic Gates

The logic circuit in figure is equivalent to

Figure

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Answer: (d)

  1. NAND gives AB‾\overline{AB}.
  2. NOR with inputs tied acts as NOT: ABAB.
  3. Final NOT: Y=AB‾Y = \overline{AB}.
  4. So the answer is (d) NAND gate.
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