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MHT CET 2026 (20 Apr, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2026 (20 Apr, Shift 1)

Q12MHT CET 2026 · 20 APR · SHIFT 1Medium

Logic Gates

The output Y of the following digital logic circuit will be '1' (one) for the inputs

Figure

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Answer: (d)

  1. Circuit: Y=A‾+B⋅CY = \overline{A} + B \cdot C.
  2. All options have A=1A = 1, so A‾=0\overline{A} = 0 and Y=B⋅CY = B \cdot C.
  3. Y=1Y = 1 needs B=1B = 1 and C=1C = 1.
  4. So the answer is (d) A=1,B=1,C=1A = 1, B = 1, C = 1.
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