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MHT CET 2026 (12 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2026 (12 May, Shift 2)

Q24MHT CET 2026 · 12 MAY · SHIFT 2Medium

Logic Gates

The output YY of the given logic circuit is similar to the output of

Figure

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Answer: (d)

  1. NOR output: A+B‾=AˉBˉ\overline{A+B} = \bar A \bar B; NAND output: AB‾=Aˉ+Bˉ\overline{AB} = \bar A + \bar B.
  2. AND of the two: Y=AˉBˉ(Aˉ+Bˉ)=AˉBˉ+AˉBˉ=AˉBˉY = \bar A \bar B(\bar A + \bar B) = \bar A \bar B + \bar A \bar B = \bar A \bar B
  3. Y=AˉBˉ=A+B‾Y = \bar A \bar B = \overline{A+B}
  4. So the answer is (d) NOR gate.
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