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MHT CET 2026 (18 Apr, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2026 (18 Apr, Shift 2)

Q14MHT CET 2026 · 18 APR · SHIFT 2Medium

Logic Gates

The output Y of the given logic circuit is

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Answer: (c)

Upper gate is NAND of $A, B$ : output $\overline{A \cdot B}$ .
Lower gate is NOR of $B, C$ : output $\overline{B + C}$ .
The OR gate adds them: $Y = \overline{(A \cdot B)} + \overline{(B + C)}$ .
So the answer is (c).

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