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MHT CET 2024 (4 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2024 (4 May, Shift 2)

Q65MHT CET 2024 · 4 MAY · SHIFT 2Medium

Logic Gates

The truth table for the given logic circuit is

Figure

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Answer: (a)

  1. Upper gate is NOR: A+B‾\overline{A + B}. Lower gate is AND: A⋅BA \cdot B. Final gate is NAND.
  2. Y=A+B‾⋅(A⋅B)‾Y = \overline{\overline{A + B} \cdot (A \cdot B)}.
  3. A+B‾\overline{A + B} and A⋅BA \cdot B can never both be 1, so their product is always 0 and Y=1Y = 1 for all inputs.
  4. Table P has Y = 1 in every row, so the answer is (a) P.
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