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MHT CET 2025 (25 Apr, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2025 (25 Apr, Shift 1)

Q39MHT CET 2025 · 25 APR · SHIFT 1Medium

Logic Gates

To get output of the following logic circuit as ' 0 ' (zero), the inputs A,B,CA, B, C should NOT be, respectively,

Figure

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Answer: (d)

  1. NOR gives A+B‾\overline{A + B}; AND with C gives Y=A+B‾⋅CY = \overline{A + B} \cdot C.
  2. Y = 1 only when A=0,B=0,C=1A = 0, B = 0, C = 1; every other input gives Y = 0.
  3. So the inputs that do NOT give 0 are 0,0,10, 0, 1.
  4. So the answer is (d).
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