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MHT CET 2024 (16 May, Shift 2) · Logic Gates

Logic Gates question from MHT CET 2024 (16 May, Shift 2)

Q59MHT CET 2024 · 16 MAY · SHIFT 2Medium

Logic Gates

To get the truth table shown from the following logic circuit, the logic gate G should be

Figure

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Answer: (c)

  1. Y=A+G(A,B)Y = A + G(A, B) and the table gives Y=1Y = 1 in every row.
  2. When A=0A = 0, G must give 1 for B=0B = 0 and B=1B = 1.
  3. NAND: 0⋅0‾=1\overline{0 \cdot 0} = 1, 0⋅1‾=1\overline{0 \cdot 1} = 1. AND and NOR fail at (0,1)(0,1); OR fails at (0,0)(0,0).
  4. So the answer is (c) NAND.
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