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MHT CET 2026 (17 Apr, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2026 (17 Apr, Shift 1)

Q16MHT CET 2026 · 17 APR · SHIFT 1Medium

Logic Gates

To get the truth table shown from the following logic circuit, the gate G should be

Figure

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Answer: (c)

  1. Y=A+G(A,B)Y = A + G(A, B). The table shows Y=AY = A in every row.
  2. So when A=0A = 0, G must give 0 for both B=0B = 0 and B=1B = 1; when A=1A = 1, Y is 1 anyway.
  3. AND: 0⋅0=00 \cdot 0 = 0, 0⋅1=00 \cdot 1 = 0. OR, NAND and NOR each give 1 in one of these rows.
  4. So the answer is (c) AND gate.
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