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MHT CET 2023 (10 May, Shift 1) · Logic Gates

Logic Gates question from MHT CET 2023 (10 May, Shift 1)

Q92MHT CET 2023 · 10 MAY · SHIFT 1Medium

Logic Gates

To obtain the truth-table shown, from the following logic circuit, the gate G should be

Figure

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Answer: (d)

  1. Y=A+G(A,B)Y = A + G(A, B). Rows with A=1A = 1 give 1 automatically.
  2. For A=0A = 0 the table needs G(0,0)=1G(0,0) = 1 and G(0,1)=0G(0,1) = 0.
  3. NOR: 0+0‾=1\overline{0 + 0} = 1, 0+1‾=0\overline{0 + 1} = 0. NAND gives 1 at (0,1)(0,1); AND and OR give 0 at (0,0)(0,0).
  4. So the answer is (d) NOR.
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